1. Field of the Invention
The present invention relates to electronic and semiconductor devices, and more particularly to light emitting devices and methods of fabricating light emitting devices.
2. Description of Related Art
Light emitting diodes and laser diodes are well known solid state electronic devices capable of generating light upon application of a sufficient voltage. Light emitting diodes and laser diodes may be generally referred to as light emitting devices (LEDs). Light emitting devices generally include a p-n junction formed in an epitaxial layer grown on a substrate such as sapphire, silicon, silicon carbide, gallium arsenide and the like. The wavelength distribution of the light generated by the LED depends on the material from which the p-n junction is fabricated and the structure of the thin epitaxial layers that include the active region of the device.
LED chips are mounted in various packages for different applications. One example of an LED based lamp product is offered by Cree Inc. as its XR-E product and combines the brightness of LED chips and rugged packaging technology well suited for solid state lighting industry. The XR-E package comprises an LED chip mounted onto a substrate along with optical, electrical and mechanical components assembled to provide 80 lm of white light at 350 mA with efficient thermal management. One important feature of these products is the electrical feed-throughs that route the device electrodes to the backside of the substrate thus making it a surface mount type device; a preferred package configuration in solid state lighting industry.
Although the XR-E products deliver 80 lm of light, there is considerable effort to further improve performance levels of existing LEDs to keep the $/lm/Watt number low. In addition of increasing the chip efficiency, the package manufacturing size and hence the cost needs to be reduced. One approach to reduce package related cost is by wafer level packaging, i.e component assembly/integration at wafer level.
To realize full component integration in semiconductor devices, an understanding of materials compatibility is important. Si is inexpensive and has good thermal, mechanical and electrical properties. Its oxide serves as an excellent dielectric layer in IC manufacturing, as well as an etch stop layer in micromachining applications for MEMS devices. However, Si's limited bandgap and its modest mobilities can limit device performance and restrict optical applications. Alternatively, gallium arsenide (GaAs) and other compound semiconductors with better bandgap characteristics or mobilities can also be used, but such materials are generally more costly.
Recent developments in wafer-bonding technology have provided the means to integrate different materials into semiconductor devices. Wafer bonding is a semiconductor manufacturing process in which two semiconductor wafers are bonded to form a single substrate having specific properties. A variety of bonding methods can be used to create integrated electronics, and to combine multifunctional components onto a single die. In particular, wafer bonding provides a means for unifying different materials in semiconductor devices, thus allowing the creation of new devices and microcomponents having properties that cannot be achieved using a single material or single material system. Wafer bonding is commonly used to form silicon-on-insulator (SOI) substrates and can also be used to bond wafers composed of different materials (e.g. GaAs on Si, SiC on Si).
The choice of wafer bonding process used to fabricate a device is dependent upon the type of device, particularly the components and materials used to build the device. For example, eutectic wafer bonding is based on the use of bonding materials that form a eutectic alloy at specific temperature conditions, and eutectic bonding media such as Au—Si, Au—Sn or Pd—Si are widely used. Eutectic bonding meets the demand for hermetic as well as vacuum sealing for many Microsystems and is frequently used for MEMS devices and advanced packaging. Eutectic wafer bonding using AuSn, for example, can provide the requisite range of thermal impedance (from junction to board) in an EZ™-type LED device (e.g. about 5-10° C./W for high power chips). However, wafer bonding with eutectic materials is currently limited to vertical device geometries where the second electrical contact is provided by a wire bond to the top of the chip. For chip scale packages (e.g. flip chips), it would be advantageous to create devices at the wafer level with both electrical contacts on the bottom of the chip, such as those described in U.S. Pat. No. 7,329,905 B2, assigned to Cree Inc. This would require electrically and thermally conducting bond medium selectively deposited to avoid electrical shorting. Alternatively, if a blanket electro-conducting bond medium is used, then additional processing steps are required to selectively etch the bond medium. Also, selective area wafer alignment bonding is slow and requires the use of costly alignment procedures.
Dielectric materials can also be used for wafer bonding. However, dielectric films are electroinsulating and typically have poor thermal characteristics such that the thermal impedance of a device bonded using dielectric material is expected to be much higher than one bonded using eutectic material. One approach to minimizing impedance is to reduce the thickness of the dielectric bond medium. However, the thickness of the bond medium is crucial to minimize stress effects during bonding of dissimilar materials, and thus there is a practical limit to how thin it can be (i.e. at least about one micron) in a conventional device.